# Semiconductor Package Types Reference (QFN, BGA, SOIC, WLCSP and more)

> Source: https://netray.co/tools/semiconductor-package-types-reference
> Publisher: Netray (netray.co), AI and integration engineering for ERP and manufacturing systems.
> Section: Free Tools

## Short answer

Lookup table of common IC package families with full names, terminal style, interconnect method and typical applications.

## Category

electronics

## Industry

Semiconductors

## Audience

- Package engineer
- OSAT planner
- Component engineer

## Tool

**Kind:** worksheet

**Mode:** reference

**Columns:**

#### Abbreviation

**Key:** abbr

**Type:** text

#### Full name

**Key:** name

**Type:** text

#### Terminal style

**Key:** terminals

**Type:** text

#### Mounting

**Key:** mount

**Type:** text

#### Notes

**Key:** note

**Type:** text

**Rows:**

#### Dual in-line package

**Abbr:** DIP

**Terminals:** Two rows of leads on opposite sides

**Mount:** Through-hole

**Note:** Common in prototyping, legacy and socketed parts

#### Small outline (integrated circuit) package

**Abbr:** SOP / SOIC

**Terminals:** Gull-wing leads on two sides

**Mount:** Surface mount

**Note:** Widely used for analog, logic and memory

#### Shrink small outline package

**Abbr:** SSOP

**Terminals:** Gull-wing leads on two sides, finer pitch

**Mount:** Surface mount

**Note:** Smaller pitch than SOIC

#### Thin shrink small outline package

**Abbr:** TSSOP

**Terminals:** Gull-wing leads on two sides, thin body

**Mount:** Surface mount

**Note:** Thin body for space constrained boards

#### Thin small outline package

**Abbr:** TSOP

**Terminals:** Leads on the two short or long sides

**Mount:** Surface mount

**Note:** Used for flash and memory devices

#### Small outline transistor

**Abbr:** SOT

**Terminals:** Three to six gull-wing leads

**Mount:** Surface mount

**Note:** Small discretes, regulators, small ICs (for example SOT-23)

#### Quad flat package

**Abbr:** QFP

**Terminals:** Gull-wing leads on four sides

**Mount:** Surface mount

**Note:** Microcontrollers, ASICs; includes LQFP and TQFP variants

#### Plastic leaded chip carrier

**Abbr:** PLCC

**Terminals:** J-leads on four sides

**Mount:** Surface mount or socket

**Note:** Older memory and logic devices

#### Quad flat no-lead

**Abbr:** QFN

**Terminals:** Pads on the underside edges

**Mount:** Surface mount

**Note:** Often has an exposed thermal pad; also called MLF or MLP

#### Dual flat no-lead

**Abbr:** DFN

**Terminals:** Pads on two sides of the underside

**Mount:** Surface mount

**Note:** Small power and analog parts

#### Land grid array

**Abbr:** LGA

**Terminals:** Flat pads in a grid on the underside

**Mount:** Surface mount or socket

**Note:** Used for processors and modules

#### Ball grid array

**Abbr:** BGA

**Terminals:** Solder balls in a grid on the underside

**Mount:** Surface mount reflow

**Note:** High pin count processors, memory, FPGAs

#### Fine-pitch BGA / chip scale package

**Abbr:** FBGA / CSP

**Terminals:** Fine-pitch solder balls

**Mount:** Surface mount reflow

**Note:** Package close to die size; common for memory and mobile

#### Wafer level chip scale package

**Abbr:** WLCSP

**Terminals:** Solder balls or bumps formed at wafer level

**Mount:** Surface mount reflow

**Note:** Package is essentially the die size; sensitive to board stress

#### Flip chip ball grid array

**Abbr:** FC-BGA

**Terminals:** Balls on the substrate, bumps on the die

**Mount:** Surface mount reflow

**Note:** Die connected face down with bumps instead of wire bonds

#### Transistor outline power packages

**Abbr:** TO-220 / TO-247

**Terminals:** Three leads with a metal tab

**Mount:** Through-hole

**Note:** Power transistors and regulators with a heat sink tab

#### Power surface mount packages

**Abbr:** DPAK / D2PAK

**Terminals:** Leads plus a large thermal tab

**Mount:** Surface mount

**Note:** Power MOSFETs and regulators

#### System in package

**Abbr:** SiP

**Terminals:** Varies by design

**Mount:** Typically surface mount

**Note:** Multiple die and passives in a single package

**Notes:** Package names and dimensions are defined by JEDEC and manufacturer drawings, and variants differ between vendors. Treat this table as an orientation guide, and always use the manufacturer package outline drawing for land patterns and thermal data.

## Content

**Intro:** IC package names are a maze of abbreviations. This reference decodes the common families, from DIP and SOIC to QFN, BGA, WLCSP and flip chip, and shows terminal style, mounting method and typical applications in one searchable table.

**Sections:**

#### How to use the reference

**Body:** Search by abbreviation or by a keyword such as thermal pad or reflow. Use it when reading a BOM, a datasheet or an OSAT quotation where only the short code appears. Export the filtered list to Excel to attach to a component engineering note or an ERP item master clean-up.

**Bullets:**

- Search the abbreviation exactly as printed on the BOM
- Check mounting to see whether the part is through-hole or reflow
- Use notes to spot thermal or board-stress considerations

#### Leaded versus no-lead versus array

**Body:** Leaded packages such as SOIC and QFP have visible leads that can be inspected after soldering. No-lead packages such as QFN and DFN have pads under the body, which saves space and improves thermal performance but needs X-ray or careful AOI. Array packages such as BGA and LGA put terminals in a grid for high pin counts and are inspected mainly by X-ray.

#### Wire bond versus flip chip

**Body:** Inside the package, the die is connected either by fine wires from die pads to the lead frame or substrate, or by bumps on a face-down die. Wire bonding is mature and flexible. Flip chip gives shorter paths, better electrical performance and higher I/O density, at higher substrate cost. The package family name does not always tell you which interconnect is used, so check the datasheet or the OSAT process flow.

#### Common mistakes

**Body:** Do not assume packages with the same abbreviation share a footprint across vendors, since body size, pitch and pad size vary. Do not mix up QFN pad pullback or exposed pad requirements when creating a land pattern. In an ERP item master, record the exact JEDEC outline or manufacturer package code, not just the family.

**Cta:** If your item master has inconsistent package fields, Netray can help clean and query them across ERP and PLM data, on your own servers.

**Faq:**

#### What is the difference between QFN and BGA?

**Answer:** A QFN has flat pads around the underside edges of the body, while a BGA has an array of solder balls across the underside. BGAs support far higher pin counts, and QFNs are simpler and cheaper for lower pin counts.

#### What does WLCSP mean?

**Answer:** Wafer level chip scale package. The package terminals are built on the wafer before dicing, so the finished package is about the same size as the die. It is compact but more sensitive to board level stress.

#### Is MLF the same as QFN?

**Answer:** MLF (micro lead frame) and MLP are vendor names for packages that are essentially QFN style no-lead packages. Check the outline drawing for the exact dimensions.

#### Where do I find the official package dimensions?

**Answer:** Use the manufacturer package outline drawing and the relevant JEDEC outline reference. Those documents define body size, pitch, pad geometry and tolerances.

## Search terms

IC package types, QFN vs BGA, semiconductor package list, SOIC TSSOP QFP difference, WLCSP package meaning, flip chip vs wire bond package, package type abbreviations

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