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Semiconductor Package Types Reference (QFN, BGA, SOIC, WLCSP and more)

IC package names are a maze of abbreviations. This reference decodes the common families, from DIP and SOIC to QFN, BGA, WLCSP and flip chip, and shows terminal style, mounting method and typical applications in one searchable table.

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Abbreviation	Full name	Terminal style	Mounting	Notes
DIP	Dual in-line package	Two rows of leads on opposite sides	Through-hole	Common in prototyping, legacy and socketed parts
SOP / SOIC	Small outline (integrated circuit) package	Gull-wing leads on two sides	Surface mount	Widely used for analog, logic and memory
SSOP	Shrink small outline package	Gull-wing leads on two sides, finer pitch	Surface mount	Smaller pitch than SOIC
TSSOP	Thin shrink small outline package	Gull-wing leads on two sides, thin body	Surface mount	Thin body for space constrained boards
TSOP	Thin small outline package	Leads on the two short or long sides	Surface mount	Used for flash and memory devices
SOT	Small outline transistor	Three to six gull-wing leads	Surface mount	Small discretes, regulators, small ICs (for example SOT-23)
QFP	Quad flat package	Gull-wing leads on four sides	Surface mount	Microcontrollers, ASICs; includes LQFP and TQFP variants
PLCC	Plastic leaded chip carrier	J-leads on four sides	Surface mount or socket	Older memory and logic devices
QFN	Quad flat no-lead	Pads on the underside edges	Surface mount	Often has an exposed thermal pad; also called MLF or MLP
DFN	Dual flat no-lead	Pads on two sides of the underside	Surface mount	Small power and analog parts
LGA	Land grid array	Flat pads in a grid on the underside	Surface mount or socket	Used for processors and modules
BGA	Ball grid array	Solder balls in a grid on the underside	Surface mount reflow	High pin count processors, memory, FPGAs
FBGA / CSP	Fine-pitch BGA / chip scale package	Fine-pitch solder balls	Surface mount reflow	Package close to die size; common for memory and mobile
WLCSP	Wafer level chip scale package	Solder balls or bumps formed at wafer level	Surface mount reflow	Package is essentially the die size; sensitive to board stress
FC-BGA	Flip chip ball grid array	Balls on the substrate, bumps on the die	Surface mount reflow	Die connected face down with bumps instead of wire bonds
TO-220 / TO-247	Transistor outline power packages	Three leads with a metal tab	Through-hole	Power transistors and regulators with a heat sink tab
DPAK / D2PAK	Power surface mount packages	Leads plus a large thermal tab	Surface mount	Power MOSFETs and regulators
SiP	System in package	Varies by design	Typically surface mount	Multiple die and passives in a single package

Package names and dimensions are defined by JEDEC and manufacturer drawings, and variants differ between vendors. Treat this table as an orientation guide, and always use the manufacturer package outline drawing for land patterns and thermal data.

Item master package field clean-up

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How to use the reference

Search by abbreviation or by a keyword such as thermal pad or reflow. Use it when reading a BOM, a datasheet or an OSAT quotation where only the short code appears. Export the filtered list to Excel to attach to a component engineering note or an ERP item master clean-up.

Search the abbreviation exactly as printed on the BOM
Check mounting to see whether the part is through-hole or reflow
Use notes to spot thermal or board-stress considerations

Leaded versus no-lead versus array

Leaded packages such as SOIC and QFP have visible leads that can be inspected after soldering. No-lead packages such as QFN and DFN have pads under the body, which saves space and improves thermal performance but needs X-ray or careful AOI. Array packages such as BGA and LGA put terminals in a grid for high pin counts and are inspected mainly by X-ray.

Wire bond versus flip chip

Inside the package, the die is connected either by fine wires from die pads to the lead frame or substrate, or by bumps on a face-down die. Wire bonding is mature and flexible. Flip chip gives shorter paths, better electrical performance and higher I/O density, at higher substrate cost. The package family name does not always tell you which interconnect is used, so check the datasheet or the OSAT process flow.

Common mistakes

Do not assume packages with the same abbreviation share a footprint across vendors, since body size, pitch and pad size vary. Do not mix up QFN pad pullback or exposed pad requirements when creating a land pattern. In an ERP item master, record the exact JEDEC outline or manufacturer package code, not just the family.

Frequently Asked Questions

What is the difference between QFN and BGA?

A QFN has flat pads around the underside edges of the body, while a BGA has an array of solder balls across the underside. BGAs support far higher pin counts, and QFNs are simpler and cheaper for lower pin counts.

What does WLCSP mean?

Wafer level chip scale package. The package terminals are built on the wafer before dicing, so the finished package is about the same size as the die. It is compact but more sensitive to board level stress.

Is MLF the same as QFN?

MLF (micro lead frame) and MLP are vendor names for packages that are essentially QFN style no-lead packages. Check the outline drawing for the exact dimensions.

Where do I find the official package dimensions?

Use the manufacturer package outline drawing and the relevant JEDEC outline reference. Those documents define body size, pitch, pad geometry and tolerances.

If your item master has inconsistent package fields, Netray can help clean and query them across ERP and PLM data, on your own servers.

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